Zsolt Tokei
Zsolt Tokei is Distinguished Member of Technical Staff Interconnects at imec. He joined imec in 1999 and since then held various technical positions in the organization. First as a process engineer and researcher in the field of copper low-k interconnects, then he headed the metal section. Later he became principal scientist, Program Director Nano-Interconnects and, in 2016, was appointed Distinguished Member of Technical Staff Interconnect. He earned a M.S. (1994) in physics from the University Kossuth in Debrecen, Hungary. In the framework of a co-directed thesis between the Hungarian University Kossuth and the French University Aix Marseille-III, he obtained his PhD (1997) in physics and materials science. From 1998 he worked at the Max-Planck Institute of Düsseldorf, Germany, as a post-doctorate researcher. From the date of joining imec he continued working on a range of interconnect issues including scaling, metallization, electrical characterization, module integration, reliability and system aspects.

Authored articles

A path to high-density front- and backside wafer connectivity
Advances in wafer-to-wafer hybrid bonding and backside technologies take CMOS 2.0 from concept to reality, offering more options for compute system scaling
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Semi-damascene metallization: inflection point in back-end-of-line processing?
A cost-effective metallization scheme to address the resistance-capacitance (RC) delay at beyond 20nm metal pitches for multiple generations
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Mitigating the thermal bottleneck in advanced interconnects
A modeling framework to accurately predict heat dissipation in the chip’s back-end-of-line
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Resistivity research uncovers thin film star material
Imec’s Zsolt Tökei discusses the latest outcome of imec's research on binary and ternary alloys for advanced interconnect metallization schemes with Silicon Semiconductor’s Phil Alsop.
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Can binary or ternary compounds beat Cu in future interconnect applications?
A unique methodology to explore alternative interconnect metals for the Ångström era.
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Imec demonstrates semi-damascene interconnects with fully self-aligned vias at 18nm metal pitch
Two-metal-level semi-damascene module yields excellent line/via resistance and reliability – a world first
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The promise of hybrid graphene/metal structures for advanced interconnects
Hybrid structures of graphene and metal are worthy candidates for extending the back-end-of-line technology roadmap beyond 1nm. This article takes a closer look at two of these hybrid schemes: a graphene-capped metal interconnect and a stack of alternating graphene/metal layers. The authors discuss the potential of using these hybrid structures as advanced interconnects, they highlight the crucial role of (engineering) the interface between the two conducting materials and list the remaining integration challenges. At the 2021 IEEE International Interconnect Technology Conference, imec presents other options for scaling the back-end-of-line.
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Logic technology scaling options for 2nm and beyond
A roadmap marked by increased synergy between advanced logic device and nano-interconnect research
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A view on the logic technology roadmap
Advancing the front-end, back-end and middle-of-line towards the 1nm technology generation
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