Zsolt Tokei

Imec fellow and incoming program director of 3D system integration
Author

Zsolt Tokei is Distinguished Member of Technical Staff Interconnects at imec. He joined imec in 1999 and since then held various technical positions in the organization. First as a process engineer and researcher in the field of copper low-k interconnects, then he headed the metal section. Later he became principal scientist, Program Director Nano-Interconnects and, in 2016, was appointed Distinguished Member of Technical Staff Interconnect. He earned a M.S. (1994) in physics from the University Kossuth in Debrecen, Hungary. In the framework of a co-directed thesis between the Hungarian University Kossuth and the French University Aix Marseille-III, he obtained his PhD (1997) in physics and materials science. From 1998 he worked at the Max-Planck Institute of Düsseldorf, Germany, as a post-doctorate researcher. From the date of joining imec he continued working on a range of interconnect issues including scaling, metallization, electrical characterization, module integration, reliability and system aspects.

Portrait of Zsolt Tokei standing with arms crossed in front of large office windows

Authored articles

Cross-section of wafer interconnects linking the front and backside

A path to high-density front- and backside wafer connectivity

19/08/2025
Page-turner
3D integration

Advances in wafer-to-wafer hybrid bonding and backside technologies take CMOS 2.0 from concept to reality, offering more options for compute system scaling

Read more
Cleanroom with researchers in white suits working beside semiconductor equipment

Semi-damascene metallization: inflection point in back-end-of-line processing?

31/10/2024
Page-turner
Interconnects

A cost-effective metallization scheme to address the resistance-capacitance (RC) delay at beyond 20nm metal pitches for multiple generations

Read more
Groene lichtpuntjes verspreid over horizontale lagen, als een abstract beeld van vloeistofgeheugen

Mitigating the thermal bottleneck in advanced interconnects

28/09/2023
Longread
Interconnects

A modeling framework to accurately predict heat dissipation in the chip’s back-end-of-line

Read more
Portrait of a researcher in front of a colorful thin-film microchip graphic and metallic lattice structure

Resistivity research uncovers thin film star material

26/09/2023
Featured in the media
CMOS: advanced & beyond

Imec’s Zsolt Tökei discusses the latest outcome of imec's research on binary and ternary alloys for advanced interconnect metallization schemes with Silicon Semiconductor’s Phil Alsop.

Read more
Researchers in cleanroom suits working with semiconductor equipment in a laboratory

Can binary or ternary compounds beat Cu in future interconnect applications?

12/10/2022
Longread
Interconnects

A unique methodology to explore alternative interconnect metals for the Ångström era.

Read more
Two cleanroom researchers in protective suits discussing work beside semiconductor equipment

Imec demonstrates semi-damascene interconnects with fully self-aligned vias at 18nm metal pitch

23/06/2022
Research update
Interconnects

Two-metal-level semi-damascene module yields excellent line/via resistance and reliability – a world first

Read more
Stylized close-up of a graphene lattice with blue and pink metallic bonds

The promise of hybrid graphene/metal structures for advanced interconnects

28/06/2021
Longread
Interconnects

Hybrid structures of graphene and metal are worthy candidates for extending the back-end-of-line technology roadmap beyond 1nm. This article takes a closer look at two of these hybrid schemes: a graphene-capped metal interconnect and a stack of alternating graphene/metal layers. The authors discuss the potential of using these hybrid structures as advanced interconnects, they highlight the crucial role of (engineering) the interface between the two conducting materials and list the remaining integration challenges. At the 2021 IEEE International Interconnect Technology Conference, imec presents other options for scaling the back-end-of-line.

Read more
Two imec researchers stand with arms crossed in front of a blurred leafy background.

Logic technology scaling options for 2nm and beyond

14/06/2021
Vision
Logic devices

A roadmap marked by increased synergy between advanced logic device and nano-interconnect research

Read more
Cross-section view of a logic chip structure with layered fins and metal interconnects

A view on the logic technology roadmap

22/09/2020
Longread
Logic devices

Advancing the front-end, back-end and middle-of-line towards the 1nm technology generation

Read more

imec in your region

Looking for information about imec's activities in different parts of the world?

United Kingdom
United States
Qatar