Advanced patterning and key process steps

Imec and its partners are working on the improved tools and processes that are indispensable for the advancement of consecutive technology nodes.

ASML lithography tool in imec’s cleanroom with technicians nearby

Imec works with the world’s leading equipment and material suppliers to develop the most advanced patterning techniques. We combine:

  • advanced imaging
  • novel patterning materials
  • new etch capabilities
  • state-of-the-art metrology

These tools and techniques are available in imec’s advanced 300mm cleanroom, resulting in a unique, vendor-neutral lab where the processes for next-generation logic and memory circuits are developed and perfected.

2026 press release: Imec unlocks lever for EUV dose reduction

Researcher in a cleanroom examines a reflective silicon wafer

Do you want regular updates on imec’s semiconductor research?

Do you develop patterning tools, resist chemicals, semiconductor materials, analysis software, semiconductor process technology tools? Or are you perfecting advanced process steps for next technology nodes? Then you’re sure to benefit from imec’s ecosystem, cleanroom and many collaboration options.

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Advanced lithography

In the frame of the Advanced Patterning Center collaboration with ASML, we’re developing next-generation EUV patterning solutions while accelerating the industrialization of EUV lithography by pro-actively analyzing and solving technical challenges related to stochastic defects, reliability and yield.

Dense array of 28nm pitch contact holes patterned in a semiconductor layer
28nm contact holes, obtained on a 0.33NA NXE:3400 full field scanner

To help do that, we’ve set up the AttoLab, where we can image at high-NA EUV dimensions and study EUV photon absorption and subsequent ionization processes at unprecedented timescales from attoseconds to picoseconds.

High NA EUV lithography: launching the industry into the angstrom era

High NA EUV lithography is crucial to extend the logic and memory technology roadmaps into sub-2nm territory.

The case for High NA EUV: unlocking the next era of chip manufacturing

Imec plays a key role in the accelerated adoption of High NA for mass manufacturing. Its pre-competitive research program brings together over 50 partners, from chip manufacturers to equipment/material suppliers and metrology experts sharing risks, costs and IP. They work with imec’s long-time experts on challenges such as mask and imaging optimization, and advanced etch and metrology.

This unmatched access to tools and expertise would be impossible without the unique collaboration between imec and ASML on High NA EUV.

High-NA EUV lithography tool being assembled in a cleanroom at the imec-ASML lab
Assembly of a High NA EUV tool in joint imec-ASML High-NA lab at ASML’s headquarters in Veldhoven, the Netherlands. Credit: ASML

In a first phase, this resulted in a joint High NA lab built around the TWINSCAN EXE:5000.

In the next phase, these activities are ramped up on the next-generation TWINSCAN EXE:5200. This latest High NA tool was installed in March 2026 as part of the imec pilot line in Leuven, supported by the European NanoIC project.

High-NA EUV lithography patterning showing dense nanoscale line arrays on a chip surface
18nm pitch Ru lines obtained with DME after single exposure High NA EUV lithography.

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Researcher in a cleanroom using a microscope at a metrology workstation

Four decades of in-fab metrology and inspection: pivotal milestones, and the road ahead

27/07/2026
Technology review
Patterning
NanoIC pilot line

Linking advances in in-fab metrology and inspection to critical periods in the patterning and logic device roadmap

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Abstract blue and purple technology panels with circuit-like patterns and glowing layers

ITF Spain

03/11/2026
Barcelona, Spain

A new chapter for deep-tech innovation

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Researchers in cleanroom suits stand beside a High NA EUV system inside a semiconductor lab.

Imec receives the world’s most advanced High NA EUV system

18/03/2026
press release
Patterning

A major milestone in propelling industry into the ångström era

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Abstract blue semiconductor chip tiles floating on a purple background

ITF USA 2026 at SEMICON® West

12/10/2026
San Francisco, USA

From silicon to systems: building the AI future The pace of AI evolution leaves little room for certainty. Yet, several trends are clear: AI agents increasingly collaborating in orchestrated ecosystems are on the rise. Physical AI is a crucial next step, including (humanoid) robots transforming our homes and workspaces. In parallel, AI – just like advances in quantum computing – could help unlock breakthroughs in fields such as physics and biology. Building the AI future starts with a solid hardware foundation – from high-performance, energy-efficient compute in the data centers to low-power, real-time inference at the edge. ITF USA at SEMICON® West presents the building blocks for shaping the AI future. On October 12 in San Francisco, we take stock of the full AI deep-tech stack: from silicon to systems, from research to manufacturing. Discover ITF USA

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