The promise of OTS-only memories for next-gen compute system architectures

The discovery of a memory effect in ovonic threshold switching (OTS) devices paves the way to a new compute express link (CXL) memory

BlurHashMicroscope cross-section of a semiconductor structure with repeating narrow contacts and 100 nm scale bar

While investigating ovonic threshold switching (OTS) devices for selector applications, researchers at imec observed an interesting phenomenon: the device can operate as a memory itself.

This OTS-only memory involves a simple and cost-effective fabrication process, is scalable to larger densities, and shows promising performance characteristics for compute express link (CXL) memory-like applications – in between DRAM and NAND.

By reading this article, originally published in EDN, you will learn:

  •  how the OTS-only memory evolved out of OTS selector device technology,
  •  how it works,
  •  and which research directions are needed to meet the specs of a CXL memory for high-performance computing applications.

Read the article in EDN.

Authors

Portrait of Daniele Garbin standing indoors at imec with a blurred lab-like background

Daniele Garbin

R&D Engineer at imec
Author

Daniele Garbin received his Ph.D. in nanoelectronics and nanotechnology from Université Grenoble Alpes, Grenoble, France, in 2015. In 2016, he joined imec, Leuven, Belgium, where he works as an R&D Engineer. His current research interests include OTS and various emerging memory device technologies.

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Portrait of Gouri Sankar Kar standing in a bright hallway beside large windows

Gouri Sankar Kar

VP R&D compute & memory device technologies at imec
Author

Gouri Sankar Kar received the PhD degree in semiconductor device physics from the Indian Institute of Technology, Khragput, India in 2002. From 2002 to 2005, he was a visiting scientist at Max Planck Institute for Solid State Research, Stuttgart, Germany, where he worked with Nobel Laureate (1985, Quantum Hall Effect) Prof. Klaus von Klitzing on quantum dot FET. In 2006, he joined Infineon/Qimonda in Dresden, Germany as lead integration engineer. There he worked on the vertical transistor for DRAM application. In 2009, he joined imec, Leuven, Belgium, where he is currently ‎distinguished member of technical staff (DMTS). In this role, he defines the strategy and vision for RRAM, DRAM-MIMCAP and STT-MRAM programs both for stand-alone and embedded applications.
 

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