Compute system architecture
Imec’s center of excellence for hardware-software-technology codesign for future compute systems, and pathfinding of optimized architectures for scalable systems in the chiplet era.
HPC and AI are disrupting every application sector – from personalized medicine through genomics to self-driving cars and intuitive human-machine interaction. The only constraint on continued innovation is the capacity of today’s compute systems.
Imec aims to solve these scaling issues by creating novel approaches to computing, connectivity, and architecture. We do this by leveraging our unique position in the R&D landscape, with expertise across the entire system and technology stack.
Read this in-depth article on how to address the scaling limitations of future computing systems
Towards post-exascale performance
Compute System Architecture (CSA) is imec’s center of excellence in enabling true hardware-software-technology codesign to architect HPC and AI systems of the future.
The goal of CSA is to develop energy-conscious, high-performance computing solutions at scale for the chiplet era. The team analyzes emerging usage models and architects compute systems capable of post-exascale performance.
CSA’s core expertise in system-level modelling, performance analysis and hardware validation enables system exploration encompassing the entire spectrum of workload complexity, modelling granularity and technology maturity.
Tailored services of CSA include early design space exploration for domain-specific system architectures in RISC-V and ARM based platforms. CSA offers efficient and effective insights through multi-fidelity performance modelling and analysis.
CSA’s collaborator base includes leading fabless companies, startups, SMEs, foundry partners, semiconductor tool vendors, and academic institutions. We also work closely with imec research labs on HPC/AI applications and innovative technologies towards future systems.
Click for more info on software-defined silicon (SDSi)
Click for more info on imec’s high-performance computing software lab
Click for more info on our research into superconducting computing
Collaborate with us for derisking and pathfinding of your compute system architecture
Leveraging its in-house expertise in scalable multi-fidelity modelling and performance analysis, imec’s CSA team helps you to perform design space exploration for your system at the architecture definition stage.
Due to imec’s close interaction with leading foundries, it grants you early knowledge on your system’s performance at different technology nodes.
Through a range of services that supplement your in-house capability, we ensure that all early performance questions at architecture definition level are explored and answered:
- system architecture definition – Design space exploration of heterogeneous multicore architectures for optimizing performance/TCO with functional validation and evaluation of design innovation.
- memory subsystem exploration – Investigation of novel, hybrid memory subsystems optimizing the performance of domain-specific hardware in the context of compute system architectures.
- virtual chiplet-based platform – System-level partitioning in a chiplet-based architecture and performance-power-area-cost trade-off analysis for optimized design of future compute systems.
- technology node selection – Evaluation of the impact of heterogeneous technology nodes for 3D/2.5D chiplet-based systems in package (SiPs) to facilitate the critical decisions in system level architecture.
Choose how you want to collaborate
We provide customized access to design space exploration for forward-looking domain-specific system architectures. You can pick a combination of flexible collaboration models:
- customer-driven system architecture exploration – We facilitate performance analysis and modelling to evaluate the system-level impact of your IP.
- domain-specific system architecture definition – We provide an early system architecture definition based on the your specifications and targeted workloads.
Unique team of global experts
Imec’s CSA team is a group of passionate researchers and engineers working on high-performance RISC-V- and ARM-based compute systems of the future. Our uniquely international team (over fifteen nationalities) comprises of multi-domain experts collaborating across imec offices in Belgium, UK, and USA.
Want to join us?
Imec.kelis: PPAC modeling of AI datacenters built for LLM training and inference
Scaling the complexity of LLMs necessitates an ever-increasing computational need from the systems that execute them. Keeping up with this need requires the ability to quickly evaluate and optimize design choices for AI datacenters.
Leveraging imec’s expertise in analytical performance modeling for high-performance computing and artificial intelligence, imec.kelis provides fast and accurate performance, power, area and cost evaluation and design space exploration.
The imec.kelis tool is validated within 12% worst case error for large scale LLM training and inference executions on Nvidia A100 and H100 systems. It returns results within seconds, allowing for truly interactive exploration.
Scientific publications
Karimov et al., “PARL: Page Allocation in Hybrid Main Memory using Reinforcement Learning”, Journal of Systems Architecture (JSA), (2024)
External linkPal et al. “System technology co-optimization for advanced integration”, Nature Reviews Electrical Engineering, (2024)
External linkGraening et al. “Cost-Performance Co-optimization for the Chiplet Era”, IEEE Electronics Packaging Technology Conference (EPTC), (2024)
External linkKundu et al. “Performance Modeling and Workload Analysis of Distributed Large Language Model Training and Inference”, 2024 IEEE International Symposium on Workload Characterization (IISWC), (2024)
External linkPerumkunnil et al. “Superconducting Array of Arrays for Acceleration of Transformers”, Workshop On Low Temperature Electronics (WOLTE), (2024)
External linkDelestrac et al. “Multi-level Analysis of GPU Utilization in ML Training Workloads”, 2024 Design, Automation & Test in Europe Conference (DATE), (2024)
External linkDelestrac et al. “Analyzing GPU Energy Consumption in Data Movement and Storage”, IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), (2024)
External linkChattopadhyay et al. “Improved Linear Decomposition of Majority and Threshold Boolean Functions”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (2023)
External linkSarda et al. “HW-Aware Mapping of Graph Neural Networks on RISC-V GPGPU: A Work-in-Progress”, Open-Source Compute Architecture Research (OSCAR), (2023)
External linkVan Delm et al. “HTVM: Efficient neural network deployment on heterogeneous TinyML platforms”, 2023 60th ACM/IEEE Design Automation Conference (DAC), (2023)
External linkSarda et al. “Optimising GPGPU Execution Through Runtime Micro-Architecture Parameter Analysis”, 2023 IEEE International Symposium on Workload Characterization (IISWC), (2023)
External linkMoolchandani et al. “AMPeD: An analytical model for performance in distributed training of transformers”, 2023 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), (2023)
External linkRisso et al. “Precision-aware Latency and Energy Balancing on Multi-Accelerator Platforms for DNN Inference”, 2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), (2023)
External linkGupta et al. "Design Technology co-optimization of 1D-1VCMA to improve read performance for SCM applications", 2023 IEEE International Symposium on Circuits and Systems (ISCAS), (2023)
External linkChamazcoti et al. "Exploring Pareto-Optimal Hybrid Main Memory Configurations Using Different Emerging Memories", IEEE Transactions on Circuits and Systems I: Regular Papers, (2023)
External linkDadras et al. "AIMC Modeling and Parameter Tuning for Layer-Wise Optimal Operating Point in DNN Inference", IEEE Access, (2023)
External linkChattopadhyay et al. "Improved Linear Decomposition of Majority and Threshold Boolean Functions", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (2023)
External linkMurthy et al. “Learn to Learn on Chip: Hardware-aware Meta-learning for Quantized Few-shot Learning at the Edge”, 2022 IEEE/ACM 7th Symposium on Edge Computing (SEC), (2022)
External linkJain et al. “Towards the next generation Heterogeneous Multi-core Multi-accelerator Architectures for Machine Learning”, Spring 2022 RISC-V Week, Location: Paris, France, (2022)
External linkGupta et al. "Design exploration of IGZO diode based VCMA array design for Storage Class Memory Applications", ESSDERC 2022 - IEEE 52nd European Solid-State Device Research Conference (ESSDERC), (2022)
External linkYang et al. "AERO: Design Space Exploration Framework for Resource-Constrained CNN Mapping on Tile-Based Accelerators", IEEE Journal on Emerging and Selected Topics in Circuits and Systems, (2022)
External linkHoushmand et al. "DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge", IEEE Journal of Solid-State Circuits, (2022)
External linkUeyoshi et al. "DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC", IEEE International Solid-State Circuits Conference (ISSCC), (2022)
External linkLaubeuf et al. "Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration", ACM Transactions on Design Automation of Electronic Systems (TODAES), (2022)
External linkCaselli et al. "Tiny ci-SAR A/D Converter for Deep Neural Networks in Analog in-Memory Computation", IEEE International Symposium on Circuits and Systems (ISCAS), (2022)
External linkBhattacharjee et al. "Home Emerging Computing: From Devices to Systems Chapter Synthesis and Technology Mapping for In-Memory Computing", book chapter in Emerging Computing: From Devices to Systems: Looking Beyond Moore and Von Neumann, (2022)
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