Trong Huynh-Bao
Trong Huynh-Bao received an M.Sc. degree from Politecnico di Torino, Italy in 2012 (summa cum laude). In 2017, he obtained a Ph.D. degree with the highest honor from imec, Leuven and Vrije Universiteit Brussel for his research on Design-Technology Co-optimization (DTCO) of vertical gate-all-around transistors for the beyond-5nm CMOS generations. Since 2017, he has been an R&D engineer at imec focusing on different aspects of DTCO for sub-10nm nodes, embedded SRAM, emerging memories, and circuit design enablers for extending Moore’s Law.
Authored articles
The vertical nanowire FET: enabler of highly dense SRAMs
Gate-all-around nanowire field effect transistors (FETs) in a vertical configuration bring many opportunities, such as the 'super-scaling' of SRAM memory cells.
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