Geert Van der Plas
Geert Van der Plas obtained a Ph.D. degree in Applied Sciences from the Katholieke Universiteit Leuven, Belgium, in 2001. He joined imec, Belgium, in 2003. He has been working on energy efficient data converter, power/signal integrity and 3D integration technologies. Currently he is program director of the XTCO Power program addressing system scaling challenges related to power delivery for high performance, energy efficient systems. In the Cross-technology co-optimization (XTCO) program, STCO/DTCO methodology is applied to align technology roadmaps with application needs. Geert’s interests are in system exploration and optimization, modeling and design enablement.
Authored articles
Chiplets: Piecing Together the Next Generation of Chips (Part I)
Bridging the gap: innovations in chiplet interconnect technology
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Imec highlights benefits of 3D-SOC design and backside interconnects for future high-performance systems
3D system-on-chip (3D SOC), enabled by electronic design automation (EDA) and 3D process technologies, is an attractive heterogeneous integration approach for addressing the memory wall in high-performance systems. Further performance gains at the system level can be achieved when the backside of one of the integrated wafers is exploited for either power delivery, signal routing or both. In this article, Dragomir Milojevic, Geert Van der Plas and Eric Beyne shed light on these promising approaches. The benefits of 3D-SOC design and of backside interconnects in specific circuits are highlighted in two papers presented at the 2021 IEEE International Electron Devices Meeting (IEDM).
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Imec demonstrates critical building blocks for a backside power delivery network
In several papers presented at the 2021 Symposia on VLSI Technology and Circuits (VLSI 2021), imec reports progress in developing enabling technologies for a backside power delivery network. First, the impact of backside wafer processing on the performance of ‘frontside’ FinFET devices was investigated. Second, the team revealed new approaches for efficient power delivery and conversion that are compatible with backside processing. And finally, the impact of backside connection on I/O performance is discussed from a system-technology co-optimization (STCO) perspective.
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