Anabela Veloso

Author

Anabela Veloso received a 5-years college degree (M.Sc.) in applied physics engineering from the Instituto Superior Técnico (IST)-Technical University of Lisbon, Portugal, in 1996. Until 2001, she worked for her Ph.D. studies on advanced magnetic read heads (Ph.D. degree in 2002 from INESC-IST, Portugal, including an internship at Storage Technology Corporation, Louisville, Colorado, USA in 2000). Since 2001, she has been working at imec, in Leuven, Belgium, where she is a principal engineer. Currently, her main research interests are in the areas of advanced CMOS device physics, characterization and technology, leading the nanowires project from the imec Core CMOS Logic program. She has authored or co-authored more than 200 papers published in peer-reviewed international conference proceedings and technical journals, and she was an IEDM Process and Manufacturing Technology (PMT) committee member in 2014-2015.

Portrait of Anabela Veloso standing in a bright office corridor

Authored articles

Abstract dark gray stacked geometric blocks suggesting a dense chip architecture

The vertical nanowire FET: enabler of highly dense SRAMs

23/08/2017

Gate-all-around nanowire field effect transistors (FETs) in a vertical configuration bring many opportunities, such as the 'super-scaling' of SRAM memory cells.

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