Steven Scheer

Steven Scheer was appointed Senior Vice President of compute technologies & systems / compute system scaling in 2024. In this role, he is responsible for driving sustainable advancements in functional and system scaling, with a focus on logic, memory, 3D integration, and advanced patterning. Steven joined imec in 2019, where he led the Advanced Patterning, Process, and Materials (APPM) organization. His work there encompassed patterning, unit process, and new materials development for logic, memory, photonics, and 3D integration. Before joining imec, Steven was an Account Technology Director with Tokyo Electron Ltd. (TEL), overseeing customer accounts in the Portland, OR area. During his 13-year tenure at TEL, he was responsible for R&D in patterning and cleaning technologies, holding management roles in the US, at TEL's factory in Kumamoto, Japan, and within the corporate R&D organization in Tokyo. Steven began his research career at IBM in Fishkill, NY, working on 90 nm and 65 nm patterning development. He holds a Ph.D. in Chemical Engineering from the University of Texas at Austin.