Geert Hellings
Geert Hellings received the PhD degree Electrical Engineering from the KU Leuven, Belgium, in 2012. He has been with imec since 2006, working on III-nitride-based detectors, high-mobility transistors, ESD and Reliability, before joining the Design-Technology-Co-Optimization Program in 2020. In 2022, he became the Program Director for the integrated DTCO Program. Currently, his research focusses on Compute Density Scaling for CFET Technologies and beyond within the imec Cross-Technology-Co-Optimization Program.
Authored articles
Performance boosters to scale monolithic CFET across multiple logic technology nodes
DTCO study supported by experimental demonstration of hybrid channel orientations which are needed for A3
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A path to high-density front- and backside wafer connectivity
Advances in wafer-to-wafer hybrid bonding and backside technologies take CMOS 2.0 from concept to reality, offering more options for compute system scaling
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Outer wall forksheet to bridge nanosheet and CFET device architectures in the logic technology roadmap
Improved manufacturability and performance compared to the earlier inner wall forksheet
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